The demand for greater memory density within a limited footprint continues. While advances in technology shrink the size of memory devices, various applications and the consumer market shrink the area the memory devices may occupy, and limit the amount of power they may consume. One solution to this situation includes stacking memory device dies vertically. For example, the memory dies may be stacked one on top of another such that multiple dies occupy the area of a single die. Stacking dies can result in a higher memory bandwidth with a smaller form factor and less power use.
According to various techniques, including High Bandwidth Memory (HBM) and Hybrid Memory Cube (HMC) arrangements, 2, 4, or up to 8 dynamic random-access-memory (DRAM) dies may be vertically stacked, and may also include a memory controller as a base layer, for example. In the various methods, the stacked memory dies may be interconnected using through-silicon-vias (TSV), micro-bumps, or other interconnection/communication schemes. The three-dimensional stack of memory dies can take the place of a single memory die on a circuit board, for example.
However, there can be a variety of challenges to implementing these stacked memory arrangements. For example, some stacking techniques can be complex and/or costly. Additionally, even while using high-yield techniques, volume manufacturing processes generally cannot completely eliminate defects. A percentage of each batch of manufactured memory dies includes defective dies. A die (D2D) stack of memory dies containing at least one defective die constitutes a defective stack. If the defective stack is discarded as waste, then many of the discarded dies in the stack are not defective. Thus, discarding the defective stack can increase the quantity of individual good dies that are discarded as waste.